Table of Contents
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8XC196NT USER'S MANUAL
Table
6-4
Bidirectional Port Pins ..................................................................................................6-4
6-5
Bidirectional Port Control and Status Registers ...........................................................6-5
6-6
Logic Table for Bidirectional Ports in I/O Mode ............................................................6-8
6-7
Logic Table for Bidirectional Ports in Special-function Mode .......................................6-8
6-8
Control Register Values for Each Configuration.........................................................6-10
6-9
Port Configuration Example .......................................................................................6-10
6-10
Port Pin States After Reset and After Example Code Execution................................6-11
6-11
Ports 3 and 4 Pins ......................................................................................................6-15
6-12
Ports 3 and 4 Control and Status Registers ...............................................................6-15
6-13
Logic Table for Ports 3 and 4 as I/O...........................................................................6-17
6-14
EPORT Pins ...............................................................................................................6-18
6-15
EPORT Control and Status Registers ........................................................................6-18
6-16
Logic Table for EPORT in I/O Mode...........................................................................6-23
6-17
Logic Table for EPORT in Address Mode ..................................................................6-23
6-18
Configuration Register Settings for EPORT Pins .......................................................6-24
6-19
EPORT Pin Status During Reset, CCB Fetch, Idle, Powerdown, and Hold ...............6-25
7-1
Serial Port Signals ........................................................................................................7-2
7-2
Serial Port Control and Status Registers......................................................................7-2
7-3
SP_BAUD Values When Using XTAL1 at 20 MHz.....................................................7-11
8-1
SSIO Port Signals ........................................................................................................8-2
8-2
SSIO Port Control and Status Registers ......................................................................8-2
8-3
Common SSIO_BAUD Values When Using XTAL1 at 20 MHz .................................8-10
9-1
Slave Port Signals ........................................................................................................9-4
9-2
Slave Port Control and Status Registers ......................................................................9-4
9-3
Master and Slave Interconnections ..............................................................................9-6
10-1
EPA and Timer/Counter Signals.................................................................................10-3
10-2
EPA Control and Status Registers .............................................................................10-3
10-3
Quadrature Mode Truth Table ....................................................................................10-8
10-4
Action Taken when a Valid Edge Occurs .................................................................10-12
10-5
Example Control Register Settings and EPA Operations.........................................10-20
10-6
EPAIPV Interrupt Priority Values ..............................................................................10-30
11-1
A/D Converter Pins.....................................................................................................11-2
11-2
A/D Control and Status Registers...............................................................................11-2
12-1
Minimum Required Signals.........................................................................................12-1
12-2
I/O Port Configuration Guide ......................................................................................12-2
13-1
Operating Mode Control Signals ................................................................................13-1
13-2
Operating Mode Control and Status Registers...........................................................13-2
14-1
Example of Internal and External Addresses .............................................................14-1
14-2
External Memory Interface Signals.............................................................................14-2
14-3
READY Signal Timing Definitions.............................................................................14-18
14-4
HOLD#, HLDA# Timing Definitions ..........................................................................14-20
14-5
Maximum Hold Latency ............................................................................................14-22
14-6
Bus-control Mode .....................................................................................................14-23
14-7
Modes 0, 1, 2, and 3 Timing Comparisons...............................................................14-36
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TABLES
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