Intel 8XC196NT User Manual page 88

public function2
extrn ?WSR
wsr equ 14h:byte
sp equ 18h:word
oseg
var1: dsw 1
var2: dsw 1
var3: dsw 1
cseg
function2:
push wsr
ldb wsr, #?WSR
add var1, var2, var3
;
;
;
ldb wsr, [sp]
add sp, #2
ret
end
******************************
The following is an example of a linker invocation to link and locate the modules and to deter-
mine the proper windowing.
RL196 MOD1.OBJ, MOD2.OBJ registers(100h-03ffh) windowsize(32)
The above linker controls tell the linker to use registers 0100–03FFH for windowing and to use
a window size of 32 bytes. (These two controls enable windowing.)
The following is the map listing for the resultant output module (MOD1 by default):
SEGMENT MAP FOR mod1(MOD1):
TYPE
----
**RESERVED*
STACK
*** GAP ***
OVRLY
OVRLY
*** GAP ***
CODE
CODE
*** GAP ***
;Prolog code for wsr
;Prolog code for wsr
;Epilog code for wsr
;Epilog code for wsr
BASE LENGTH ALIGNMENT
---- ------ ---------
0000H 001AH
001AH 0006H WORD
0020H 00E0H
0100H 0006H WORD
0106H 0006H WORD
010CH 1F74H
2080H 0011H BYTE
2091H 0011H BYTE
20A2H DF5EH
MEMORY PARTITIONS
MODULE NAME
-----------
MOD2
MOD1
MOD2
MOD1
4-21