Intel 8XC196NT User Manual page 462

Table A-8. Instruction Lengths and Hexadecimal Opcodes (Continued)
Mnemonic
Length
DIV
DIVB
DIVU
DIVUB
MUL (2 ops)
MUL (3 ops)
MULB (2 ops)
MULB (3 ops)
MULU (2 ops)
MULU (3 ops)
MULUB (2 ops)
MULUB (3 ops)
Mnemonic
Length
AND (2 ops)
AND (3 ops)
ANDB (2 ops)
ANDB (3 ops)
NEG
NEGB
NOT
NOTB
OR
ORB
XOR
XORB
NOTES:
1. Indirect normal and indirect autoincrement share the same opcodes, as do short- and long-indexed
modes. Because word registers always have even addresses, the address can be expressed in the
upper seven bits; the least-significant bit determines the addressing mode. Indirect normal and short-
indexed modes make the second byte of the instruction even (LSB = 0). Indirect autoincrement and
long-indexed modes make the second byte odd (LSB = 1).
2. For indexed instructions, the first column lists instruction lengths as S / L , where S is the short-indexed
instruction length and L is the long-indexed instruction length.
3. For the SCALL and SJMP instructions, the three least-significant bits of the opcode are concatenated
with the eight bits to form an 11-bit, 2's complement offset.
Arithmetic (Group II)
Direct Immediate
Opcode Length
4 FE 8C 5
4 FE 9C 4
3 8C 4
3 9C 3
4 FE 6C 5
5 FE 4C 6
4 FE 7C 4
5 FE 5C 5
3 6C 4
4 4C 5
3 7C 3
4 5C 4
Logical
Direct Immediate
Opcode Length
3 60 4
4 40 5
3 70 3
4 50 4
2 03 —
2 13 —
2 02 —
2 12 —
3 80 4
3 90 3
3 84 4
3 94 3
INSTRUCTION SET REFERENCE
Indirect
(Note 1)
Opcode Length Opcode
FE 8D 4 FE 8E
FE 9D 4 FE 9E
8D 3 8E
9D 3 9E
FE 6D 4 FE 6E
FE 4D 5 FE 4E
FE 7D 4 FE 7E
FE 5D 5 FE 5E
6D 3 6E
4D 4 4E
7D 3 7E
5D 4 5E
Indirect
(Note 1)
Opcode Length Opcode
61 3 62
41 4 42
71 3 72
51 4 52
— — —
— — —
— — —
— — —
81 3 82
91 3 92
85 3 86
95 3 96
Indexed
(Notes 1, 2)
Length
Opcode
S/L
5/6 FE 8F
5/6 FE 9F
4/5 8F
4/5 9F
5/6 FE 6F
6/7 FE 4F
5/6 FE 7F
6/7 FE 5F
4/5 6F
5/6 4F
4/5 7F
5/6 5F
Indexed
(Notes 1, 2)
Length
Opcode
S/L
4/5 63
5/6 43
4/5 73
5/6 53
— —
— —
— —
— —
4/5 83
4/5 93
4/5 87
4/5 97
A-53