Intel 8XC196NT User Manual page 487

8XC196NT USER'S MANUAL
Name Type
PBUS.15:0 I/O
PMODE.3:0 I
PROG# I
O
PVER
RD# O
READY I
B-10
Table B-4. Signal Descriptions (Continued)
Address/Command/Data Bus
During slave programming, ports 3 and 4 serve as a bidirectional port with
open-drain outputs to pass commands, addresses, and data to or from the
device. Slave programming requires external pull-up resistors.
During auto programming and ROM-dump, ports 3 and 4 serve as a regular
system bus to access external memory. P4.6 and P4.7 are left unconnected;
P1.1 and P1.2 serve as the upper address lines.
Slave programming:
PBUS.7:0 are multiplexed with AD7:0, SLP7:0, and P3.7:0.
PBUS.15:8 are multiplexed with AD15:8 and P4.7:0.
Auto programming:
PBUS.7:0 are multiplexed with AD7:0, SLP7:0, and P3.7:0.
PBUS.13:8 are multiplexed with AD13:8 and P4.5:0; PBUS15:14 are
multiplexed with P1.2:1.
Programming Mode Select
Determines the programming mode. PMODE is sampled after a device reset
and must be static while the part is operating. (Table 15-6 on page 15-13 lists
the PMODE values and programming modes.)
PMODE.3:0 are multiplexed with P0.7:4 and ACH7:4.
Programming Start
During programming, a falling edge latches data on the PBUS and begins
programming, while a rising edge ends programming. The current location is
programmed with the same data as long as PROG# remains asserted, so the
data on the PBUS must remain stable while PROG# is active.
During a word dump, a falling edge causes the contents of an OTPROM
location to be output on the PBUS, while a rising edge ends the data transfer.
PROG# is multiplexed with P2.2 and EXTINT.
Program Verification
During slave or auto programming, PVER is updated after each programming
pulse. A high output signal indicates successful programming of a location,
while a low signal indicates a detected error.
PVER is multiplexed with P2.0 and TXD.
Read
Read-signal output to external memory. RD# is asserted only during external
memory reads.
RD# is multiplexed with P5.3 and SLPRD#.
Ready Input
This active-high input signal is used to lengthen external memory cycles for
slow memory by generating wait states in addition to the wait states that are
generated internally.
When READY is high, CPU operation continues in a normal manner with wait
states inserted as programmed in the chip configuration registers. READY is
ignored for all internal memory accesses.
READY is multiplexed with P5.6.
Description