Table of Contents
Advertisement
2.5.4
Slave Port
The slave port offers an alternative for communication between two CPU devices. Traditionally,
system designers have had three alternatives for achieving this communication — a serial link, a
parallel bus without a dual-port RAM (DPRAM), or a parallel bus with a DPRAM to hold shared
data.
A serial link, the most common method, has several advantages: it uses only two pins from each
device, it needs no hardware protocol, and it allows for error detection before data is stored. How-
ever, it is relatively slow and involves software overhead to differentiate data, addresses, and
commands. A parallel bus increases communication speed, but requires more pins and a rather
involved hardware and software protocol. Using a DPRAM offers software flexibility between
master and slave devices, but the hardware interconnect uses a demultiplexed bus, which requires
even more pins than a simple parallel connection does. The DPRAM is also costly, and error de-
tection can be difficult. The SSIO offers a simple means for implementing a serial link. The mul-
tiplexed address/data bus can be used to implement a parallel link, with or without a DPRAM.
The slave port offers a fourth alternative.
The slave port offers the advantages of the traditional methods, without their drawbacks. It brings
the DPRAM on-chip. With this configuration, an external (master) processor can simply read
from and write to the on-chip memory of the 8XC196 (slave) device. The slave port requires more
pins than a serial link does, but fewer than the number used for a parallel bus. It requires no hard-
ware protocol, and it can interface with either a multiplexed or a demultiplexed bus. The master
simply reads or writes as if there were a DPRAM device on the bus. Data error detection can be
handled through the software. See Chapter 9, "Slave Port," for details.
2.5.5
Event Processor Array (EPA) and Timer/Counters
The event processor array (EPA) performs high-speed input and output functions associated with
its timer/counters. In the input mode, the EPA monitors an input for signal transitions. When an
event occurs, the EPA records the timer value associated with it. This is a capture event. In the
output mode, the EPA monitors a timer until its value matches that of a stored time value. When
a match occurs, the EPA triggers an output event, which can set, clear, or toggle an output pin.
This is a compare event. Both capture and compare events can initiate interrupts, which can be
serviced by either the interrupt controller or the PTS.
Timer 1 and timer 2 are both 16-bit up/down timer/counters that can be clocked internally or ex-
ternally. Each timer/counter is called a timer if it is clocked internally and a counter if it is clocked
externally. See Chapter 10, "Event Processor Array (EPA)," for additional information on the
EPA and timer/counters.
ARCHITECTURAL OVERVIEW
2-9
Advertisement
Table of Contents
