Intel Agilex Power And I/O State Sequencing; Overview; Power-Up Sequence Requirements - Intel Agilex User Manual

UG-20215 | 2019.04.02
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3. Intel Agilex Power and I/O State Sequencing

3.1. Overview

The Intel Agilex devices require a specific power-up sequence.
This section describes several power management options and discusses proper I/O
management during device power up and power down. Design your power supply
solution to properly control the complete power sequence. The requirements in this
section must be followed to prevent unpredictable current draw to the FPGA device,
which can potentially impact the I/O functionality.

3.2. Power-Up Sequence Requirements

The power rails in the Intel Agilex devices are divided into three groups.
The following figure shows the voltage groups of the Intel Agilex devices and their
required power-up sequence.
Figure 2. Power-Up Sequence for the Intel Agilex Devices
Note: V is not in any of the groups below. V
CCBAT
requirements. V
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Group 1
Group 1
Group 2
Group 3
holds the content of the security keys.
CCBAT
Group 2 Group 3
90% of
Nominal
Voltage
90% of
Nominal
Voltage
does not have any sequence
CCBAT
ISO
9001:2015
Registered