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This appendix provides reference information about the device registers. Table C-1 lists the mod-
ules and major components of the device with their related configuration and status registers. Ta-
ble C-2 lists the registers, arranged alphabetically by mnemonic, along with their names,
addresses, and reset values. Following the tables, individual descriptions of the registers are ar-
ranged alphabetically by mnemonic.
A/D Converter
AD_COMMAND
AD_RESULT
AD_TEST
AD_TIME
Extended Port
EP_DIR
EP_MODE
EP_PIN
EP_REG
Serial Port
SBUF_RX
SBUF_TX
SP_BAUD
SP_CON
SP_STATUS
Table C-1. Modules and Related Registers
Chip Configuration
CCR0
CCR1
CCR2
PPW (or SP_PPW)
USFR
I/O Ports
P x _DIR ( x = 1, 2, 5, 6)
P x _MODE ( x = 1, 2, 5, 6)
P x _PIN ( x = 0–6)
P x _REG ( x = 1–6)
P34_DRV
Slave Port
SLP_CMD
SLP_CON
SLP_STAT
APPENDIX C
REGISTERS
CPU
ONES_REG
COMP x _CON ( x = 0–1)
COMP x _TIME ( x = 0–1)
PSW
SP
EPA_MASK
ZERO_REG
EPA_MASK1
EPA_PEND
EPA_PEND1
EPAIPV
EPA x _CON ( x = 0–9)
EPA x _TIME ( x = 0–9)
Interrupts and PTS
INT_MASK
IRAM_CON
INT_MASK1
WSR
INT_PEND
INT_PEND1
PTSSEL
PTSSRV
Synch. Serial Port
( x = 0–1)
TIMER x
SSIO_BAUD
SSIO x _BUF
T x CONTROL
SSIO x _CON
WATCHDOG
EPA
Memory Control
Timers
( x = 1–2)
C-1
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