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8XC196NT USER'S MANUAL
4.5
FETCHING CODE AND DATA IN THE 1-MBYTE AND 64-KBYTE MODES
This section describes how the device fetches instructions and accesses data in the 1-Mbyte and
64-Kbyte modes. When the device leaves reset, the MODE64 bit (CCB2.1) selects the 1-Mbyte
or 64-Kbyte mode. The mode cannot be changed until the next reset.
4.5.1
Fetching Instructions
The 24-bit program counter (Figure 4-7) consists of the 8-bit extended program counter (EPC)
concatenated with the 16-bit master program counter (PC). It holds the address of the next in-
struction to be fetched. The page number of the instruction is in the EPC. In 1-Mbyte mode, the
EPC can have any 8-bit value. However, only the four LSBs of the EPC are implemented exter-
nally, as EPORT pins A19:16. This means that in the 1-Mbyte mode, the device can fetch code
from any page in the 1-Mbyte address space: 00H–0FH and FFH (FFH overlays 0FH). In 64-
Kbyte mode, the EPC is fixed at FFH, which limits program memory to page FFH (and 0FH).
4.5.2
Accessing Data
Internally, data addresses have 24 bits (Figure 4-8 on page 4-25). The lower 16 bits are supplied
by the 16-bit data address register. The upper 8 bits (the page number) come from different sourc-
es for nonextended and extended instructions. ("EPORT Operation" on page 6-19 describes how
the page number is output to the EPORT pins.)
For nonextended instructions, the EP_REG register provides the page number. Data and constants
in this page are called near data and near constants.
For compatibility with current and future programming tools, EP_REG must
contain 00H.
Data outside the page specified by EP_REG is called far data. To access far data, you must use
extended instructions. For extended instructions, the CPU provides the page number.
4-24
EPC
23
16 15
Figure 4-7. The 24-bit Program Counter
NOTE
PC
0
A2513-03
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