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If the device is reset while in hold, bus contention can occur. For example, a CPU-only device
(80C196NT) would try to fetch the chip configuration byte from external memory after RESET#
was brought high. Bus contention would occur because both the external device and the micro
controller would attempt to access memory. One solution is to use the RESET# signal as the sys-
tem reset; then all bus masters (including the device) are reset at once. Chapter 12, "Minimum
Hardware Considerations," shows system reset circuit examples.
14.7 BUS-CONTROL MODES
The ALE and WR bits (CCR0.3 and CCR0.2) define which bus-control signals will be generated
during external read and write cycles. Table 14-6 lists the four bus-control modes and shows the
CCR0.3 and CCR0.2 settings for each.
.
Bus-control Mode
Standard Bus-control Mode
Write Strobe Mode
Address Valid Strobe Mode
Address Valid with Write Strobe Mode
14.7.1 Standard Bus-control Mode
In the standard bus-control mode, the device generates the standard bus-control signals: ALE,
RD#, WR#, and BHE# (see Figure 14-10). ALE is asserted while the address is driven, and it can
be used to latch the address externally. RD# is asserted for every external memory read, and WR#
is asserted for every external memory write. When asserted, BHE# selects the bank of memory
that is addressed by the high byte of the data bus.
INTERFACING WITH EXTERNAL MEMORY
Table 14-6. Bus-control Mode
Bus-control Signals
ALE, RD#, WR#, BHE#
ALE, RD#, WRL#, WRH#
ADV#, RD#, WR#, BHE#
ADV#, RD#, WRL#, WRH#
CCR0.3
CCR0.2
(ALE)
(WR)
1
1
1
0
0
1
0
0
14-23
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