Intel 8XC196NT User Manual page 526

INT_MASK
The interrupt mask (INT_MASK) register enables or disables (masks) individual interrupt requests.
(The EI and DI instructions enable and disable servicing of all maskable interrupts.) INT_MASK is the
low byte of the processor status word (PSW); therefore, PUSHF or PUSHA saves this register on the
stack and POPF or POPA restores it.
7
IBF OBE
Bit
Number
7:0 Setting a bit enables the corresponding interrupt.
The standard interrupt vector locations are as follows:
Bit Mnemonic Interrupt
IBF
OBE
AD
EPA0
EPA1
EPA2
EPA3
†
EPA x
†
EPA 4–9 capture/compare channel events, EPA 0–1 compare channel events, EPA 0–9
capture/compare overruns, and timer overflows can generate this multiplexed interrupt.
The EPA mask and pending registers decode the EPA x interrupt. Write the EPA mask
registers (EPA_MASK and EPA_MASK1) to enable the interrupt sources; read the EPA
pending registers (EPA_PEND and EPA_PEND1) to determine which source caused the
interrupt.
AD EPA0
Function
Slave Port Input Buffer Full
Slave Port Output Buffer Empty
A/D Conversion Complete
EPA Capture/Compare Channel 0
EPA Capture/Compare Channel 1
EPA Capture/Compare Channel 2
EPA Capture/Compare Channel 3
Multiplexed EPA
Address:
Reset State:
EPA1 EPA2
Standard Vector
FF200EH
FF200CH
FF200AH
FF2008H
FF2006H
FF2004H
FF2002H
FF2000H
REGISTERS
INT_MASK
0008H
00H
0
EPA x
EPA3
C-31