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T2CONTROL
The timer 2 control (T2CONTROL) register determines the clock source, counting direction, and count
rate for timer 2.
7
CE
UD
Bit
Bit
Number
Mnemonic
7
CE
6
UD
5:3
M2:0
2:0
P2:0
Figure 10-9. Timer 2 Control (T2CONTROL) Register
M2
M1
Counter Enable
This bit enables or disables the timer. From reset, the timers are
disabled and not free running.
0 = disables timer
1 = enables timer
Up/Down
This bit determines the timer counting direction, in selected modes (see
mode bits, M2:0).
0 = count down
1 = count up
EPA Clock Direction Mode Bits.
These bits determine the timer clocking source and direction source
M2
M1
M0
Clock Source
0
0
0
F
/4
OSC
X
0
1
T2CLK Pin
0
1
0
F
/4
OSC
0
1
1
T2CLK Pin
1
0
0
timer 1 overflow
1
1
0
timer 1
1
1
1
quadrature clocking using T2CLK and T2DIR pins
†
If an external clock is selected, the timer counts on both the rising and
falling edges of the clock.
EPA Clock Prescaler Bits
These bits determine the clock prescaler value.
P2 P1
P0
Prescaler
0
0
0
divide by 1 (disabled)
0
0
1
divide by 2
0
1
0
divide by 4
0
1
1
divide by 8
1
0
0
divide by 16
1
0
1
divide by 32
1
1
0
divide by 64
1
1
1
reserved
†
At 20 MHz.
EVENT PROCESSOR ARRAY (EPA)
Address:
Reset State:
M0
P2
Function
Direction Source
UD bit (T2CONTROL.6)
†
UD bit (T2CONTROL.6)
T2DIR Pin
†
T2DIR Pin
UD bit (T2CONTROL.6)
same as timer 1
Resolution
200 ns
400 ns
800
1.6 µs
3.2 µs
6.4 µs
12.8 µs
—
1F9CH
00H
0
P1
P0
†
10-19
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