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Table 14-2. External Memory Interface Signals (Continued)
Function
Type
Name
BHE#
O
Byte High Enable
The chip configuration register 0 (CCR0) determines whether this pin
functions as BHE# or WRH#. CCR0.2=1 selects BHE#; CCR0.2=0
selects WRH#.
During 16-bit bus cycles, this active-low output signal is asserted for
word reads and writes and high-byte reads and writes to external
memory. BHE# indicates that valid data is being transferred over the
upper half of the system data bus. BHE#, in conjunction with AD0,
indicates the memory byte that is being transferred over the system
bus:
BHE#
0
0
1
BREQ#
O
Bus Request
This active-low output signal is asserted during a hold cycle when
the bus controller has a pending external memory cycle.
The device can assert BREQ# at the same time as or after it asserts
HLDA#. Once it is asserted, BREQ# remains asserted until HOLD#
is removed.
You must enable the bus-hold protocol before using this signal (see
"Enabling the Bus-hold Protocol" on page 14-21).
BUSWIDTH
I
Bus Width
The chip configuration register bits, CCR0.1 and CCR1.2, along with
the BUSWIDTH pin, control the data bus width. When both CCR bits
are set, the BUSWIDTH signal selects the external data bus width.
When only one CCR bit is set, the bus width is fixed at either 16 or 8
bits, and the BUSWIDTH signal has no effect.
CCR0.1 CCR1.2 BUSWIDTH
0
1
1
1
CLKOUT
O
Clock Output
Output of the internal clock generator. The CLKOUT frequency is ½
the oscillator frequency input (XTAL1). CLKOUT has a 50% duty
cycle.
INTERFACING WITH EXTERNAL MEMORY
Description
AD0 Byte(s) Accessed
0
both bytes
1
high byte only
0
low byte only
1
N/A
fixed 8-bit data bus
0
N/A
fixed 16-bit data bus
1
high
16-bit data bus
1
low
8-bit data bus
Multiplexed
With
P5.5/WRH#
P2.3
P5.7
P2.7
14-3
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