Intel 8XC196NT User Manual page 588

JH instruction, A-3, A-5, A-23, A-50, A-57, A-65
JLE instruction, A-3, A-5, A-23, A-50, A-57, A-65
JLT instruction, A-3, A-5, A-24, A-50, A-57, A-65
JNC instruction, A-2, A-5, A-24, A-50, A-57,
A-65
JNE instruction, A-2, A-5, A-24, A-50, A-57, A-65
JNH instruction, A-2, A-5, A-25, A-50, A-57,
A-65
JNST instruction, A-2, A-5, A-25, A-50, A-57,
A-65
JNV instruction, A-2, A-5, A-25, A-50, A-57,
A-65
JNVT instruction, A-2, A-5, A-26, A-50, A-57,
A-65
JST instruction, A-3, A-5, A-26, A-50, A-57, A-65
Jump instructions, A-63
conditional, A-5, A-57, A-65
unconditional, A-56
JV instruction, A-3, A-5, A-26, A-50, A-57, A-65
JVT instruction, A-3, A-5, A-27, A-50, A-57, A-65
L
Latency‚ See bus-hold protocol‚ interrupts
LCALL instruction, A-3, A-27, A-51, A-56, A-63,
A-64
LD instruction, A-2, A-27, A-49, A-55, A-62
LDB instruction, A-2, A-28, A-49, A-55, A-62
LDBSE instruction, A-3, A-28, A-49, A-55, A-62
LDBZE instruction, A-3, A-28, A-49, A-55, A-62
Level-sensitive input, B-4
Literature, 1-11
LJMP instruction, A-2, A-28, A-51, A-56, A-63
Logical instructions, A-53, A-60
LONG-INTEGER, defined, 3-4
Lookup tables, software protection, 3-14
M
Manual contents, summary, 1-1
Manuals, online, 1-10
Measurements, defined, 1-5
Memory bus, 2-5
Memory configuration, examples, 4-28–4-33
Memory controller, 2-3, 2-5
Memory mapping
auto programming mode, 15-27
serial port programming mode, 15-33
Memory modes, 4-1–4-35
Memory partitions
OTPROM, 15-2
program memory, 15-2
special-purpose memory, 15-2
Memory protection, 15-3–15-7
CCR security-lock bits, 15-17
UPROM security bits, 15-7
Memory, external, 14-1–14-42
interface signals, 14-2
See also address/data bus, bus controller,
bus-control modes, bus-control
signals, bus-hold protocol,
bus-width, BUSWIDTH, CCRs,
ready control, timing, wait states
Memory, reserved, 4-6, 4-7
Microcode engine, 2-3
Miller effect, 12-8
Mode 0
bus-timing mode, 14-36
SIO port mode, 7-4, 7-5
Mode 1
bus-timing mode, 14-36
SIO port mode, 7-5, 7-6
Mode 2
bus-timing mode, 14-37
SIO port mode, 7-5, 7-6, 7-7
Mode 3
bus-timing mode, 14-36
SIO port mode, 7-5, 7-7
MODE64 bit, 4-24, 4-26
Modified quick-pulse algorithm, 15-9
MUL instruction, A-29, A-51, A-53, A-60
MULB instruction, A-29, A-51, A-53, A-60
Multiprocessor communications, 2-8, 2-9
methods, 2-9, 9-1
SIO port, 7-6, 7-7
slave port, 9-1
MULU instruction, A-3, A-30, A-47, A-48, A-51,
A-53, A-60
MULUB instruction, A-3, A-30, A-47, A-48,
A-53, A-60
N
Naming conventions, 1-3–1-4
NEG instruction, A-2, A-31, A-46, A-53, A-60
Negative (N) flag, A-4, A-5, A-22, A-23, A-24
NEGB instruction, A-2, A-31, A-46, A-53, A-60
INDEX
Index-7