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8XC196NT USER'S MANUAL
64-Kbyte or 1-Mbyte Mode
Execution
Interrupt
Interrupt
Pending Bit
Response Time
PTS Mode
Single transfer mode
register/register
memory/register
memory/memory
Block transfer mode
register/register
memory/register
memory/memory
A/D scan mode
register/register
register/memory
PWM remap mode
PWM toggle mode
†
Register indicates an access to the register file or peripheral SFR. Memory indicates
an access to a memory-mapped register, I/O, or memory. See Table 4-1 on page 4-4 for
address information.
5.5
PROGRAMMING THE INTERRUPTS
The PTS select register (PTSSEL) selects either PTS service or a standard software interrupt ser-
vice routine for each of the maskable interrupt requests (see Figure 5-4). The interrupt mask reg-
isters, INT_MASK and INT_MASK1, enable or disable (mask) individual interrupts (see Figures
5-5 and 5-6). With the exception of the nonmaskable interrupt (NMI) bit (INT_MASK1.7), set-
ting a bit enables the corresponding interrupt source and clearing a bit disables the source.
5-10
4
3
2
1
39
Ending
"NORML"
Instruction
Set
Latency Time
43 State Times
64-Kbyte or 1-Mbyte Mode
Figure 5-3. PTS Interrupt Response Time
Table 5-4. Execution Times for PTS Cycles
†
18 per byte or word transfer + 1
†
21 per byte or word transfer + 1
†
24 per byte or word transfer + 1
†
13 + 7 per byte or word transfer (1 minimum)
†
16 + 7 per byte or word transfer (1 minimum)
†
19 + 7 per byte or word transfer (1 minimum)
†
21
†
25
15
15
End
Vector to PTS
"NORML"
Control Block
PTS Interrupt Routine
Cleared
Execution Time (in State Times)
PTS
PTS
A0262-02
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