Intel 8XC196NT User Manual page 254

EPA x _CON
x = 0–9
The EPA control (EPA x _CON) registers control the functions of their assigned capture/compare
channels. The registers for EPA0, EPA2, and EPA4–9 are identical. The registers for EPA1 and EPA3
have an additional bit, the remap bit. This added bit (bit 8) requires an additional byte, so EPA1_CON
and EPA3_CON must be addressed as words, while the others can be addressed as bytes.
15
x = 1, 3 —
7
TB
7
x = 0, 2, 4–9 TB
Bit Bit
Number Mnemonic
†
15:9 —
†
8 RM
7 TB
†
These bits apply to the EPA1_CON and EPA3_CON registers only.
Figure 10-10. EPA Control (EPA x _CON) Registers
— — —
CE M1 M0
CE M1 M0
Reserved; always write as zeros.
Remap Feature
The remap feature applies to the compare mode of the EPA1 and EPA3
only.
When the remap feature of EPA1 is enabled, EPA capture/compare
channel 0 shares output pin EPA1 with EPA capture/compare channel 1.
When the remap feature of EPA3 is enabled, EPA capture/compare
channel 2 shares output pin EPA3 with EPA capture/compare channel 3.
0 = remap feature disabled
1 = remap feature enabled
Time Base Select
Specifies the reference timer.
0 = timer 1 is the reference timer and timer 2 is the opposite timer
1 = timer 2 is the reference timer and timer 1 is the opposite timer
A compare event (start of an A/D conversion; clearing, setting, or toggling
an output pin; and/or resetting either timer) occurs when the reference
timer matches the time programmed in the event-time register.
When a capture event (falling edge, rising edge, or an edge change on
the EPA x pin) occurs, the reference timer value is saved in the EPA event-
time register (EPA x _TIME).
EVENT PROCESSOR ARRAY (EPA)
Address: See Table 10-2 on
Reset State: F700H ( x = 1 & 3)
00H( x = 0, 2, 4–9)
— —
RE AD ROT
RE AD ROT
Function
page 10-3
8
— RM
0
ON/RT
0
ON/RT
10-21