Intel 8XC196NT User Manual page 517

8XC196NT USER'S MANUAL
EPA_MASK1
EPA_MASK1
The EPA interrupt mask 1 (EPA_MASK1) register enables or disables (masks) interrupts associated
with the multiplexed EPA x interrupt.
7
— —
Bit
Number
7:4 Reserved; for compatibility with future devices, write zeros to these bits.
3:0 Setting a bit enables the corresponding interrupt as a multiplexed EPA x interrupt source.
The multiplexed EPA x interrupt is enabled by setting its interrupt enable bit in the
interrupt mask register (INT_MASK.0 = 1).
C-22
— — COMP0
Function
Address:
Reset State:
COMP1 OVRTM1 OVRTM2
1FA4H
00H
0