Generating A Hardware Reset; Asserting The External Interrupt Signal - Intel 8XC196NT User Manual

8XC196NT USER'S MANUAL
13.4.3.2

Generating a Hardware Reset

The device will exit powerdown if RESET# is asserted. If the design uses an external clock input
signal rather than the on-chip oscillator, RESET# must remain low for at least 16 state times. If
the design uses the on-chip oscillator, then RESET# must be held low until the oscillator has sta-
bilized.
13.4.3.3

Asserting the External Interrupt Signal

The final way to exit powerdown mode is to assert the external interrupt signal (EXTINT) for at
least 50 ns. Although EXTINT is normally a sampled input, the powerdown circuitry uses it as a
level-sensitive input. The interrupt need not be enabled to bring the device out of powerdown, but
the pin must be configured as a special-function input (see "Bidirectional Port Pin Configura-
tions" on page 6-9). Figure 13-2 shows the power-up and powerdown sequence when using an
external interrupt to exit powerdown.
When an external interrupt brings the device out of powerdown mode, the corresponding pending
bit is set in the interrupt pending register. If the interrupt is enabled, the device executes the in-
terrupt service routine, then fetches and executes the instruction following the IDLPD #2 instruc-
tion. If the interrupt is disabled (masked), the device fetches and executes the instruction
following the IDLPD #2 instruction and the pending bit remains set until the interrupt is serviced
or software clears the pending bit.
XTAL1
CLKOUT
PH1
Internal Powerdown
Signal
EXTINT
V
PP
Timeout
(Internal)
Figure 13-2. Power-up and Powerdown Sequence When Using an External Interrupt
13-6
A0078-01