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Figure
11-11
Terminal-based A/D Conversion Characteristic .......................................................11-19
12-1
Minimum Hardware Connections ...............................................................................12-3
12-2
Power and Return Connections .................................................................................12-4
12-3
On-chip Oscillator Circuit............................................................................................12-6
12-4
External Crystal Connections .....................................................................................12-7
12-5
External Clock Connections .......................................................................................12-8
12-6
External Clock Drive Waveforms................................................................................12-8
12-7
Reset Timing Sequence .............................................................................................12-9
12-8
Internal Reset Circuitry .............................................................................................12-10
12-9
Minimum Reset Circuit .............................................................................................12-11
12-10
Example System Reset Circuit .................................................................................12-11
13-1
Clock Control During Power-saving Modes................................................................13-3
13-2
Power-up and Powerdown Sequence When Using an External Interrupt ..................13-6
13-3
External RC Circuit.....................................................................................................13-7
13-4
Typical Voltage on the V
14-1
Chip Configuration 0 (CCR0) Register .......................................................................14-6
14-2
Chip Configuration 1 (CCR1) Register .......................................................................14-8
14-3
Chip Configuration 2 (CCR2) Register .....................................................................14-10
14-4
Multiplexing and Bus Width Options.........................................................................14-11
14-5
BUSWIDTH Timing Diagram ....................................................................................14-12
14-6
Timings for 16-bit Buses...........................................................................................14-14
14-7
Timings for 8-bit Buses.............................................................................................14-16
14-8
READY Timing Diagram...........................................................................................14-19
14-9
HOLD#, HLDA# Timing ............................................................................................14-20
14-10
Standard Bus Control ...............................................................................................14-24
14-11
Decoding WRL# and WRH#.....................................................................................14-24
14-12
8-bit System with Flash and RAM ............................................................................14-25
14-13
16-bit System with Dynamic Bus Width....................................................................14-26
14-14
Write Strobe Mode ...................................................................................................14-27
14-15
16-bit System with Single-byte Writes to RAM .........................................................14-28
14-16
Address Valid Strobe Mode......................................................................................14-29
14-17
Comparison of ALE and ADV# Bus Cycles ..............................................................14-30
14-18
8-bit System with Flash ............................................................................................14-31
14-19
16-bit System with Flash ..........................................................................................14-32
14-20
Timings of Address Valid with Write Strobe Mode ...................................................14-33
14-21
16-bit System with RAM ...........................................................................................14-34
14-22
Modes 0, 1, 2, and 3 Timings ...................................................................................14-35
14-23
Mode 1 System Bus Timing......................................................................................14-37
14-24
Mode 2 System Bus Timing......................................................................................14-38
14-25
System Bus Timing ..................................................................................................14-39
15-1
Unerasable PROM (USFR) Register..........................................................................15-7
15-2
Programming Pulse Width (PPW or SP_PPW) Register............................................15-9
15-3
Modified Quick-pulse Algorithm................................................................................15-10
15-4
Pin Functions in Programming Modes......................................................................15-11
FIGURES
Pin While Exiting Powerdown.........................................13-8
PP
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