Intel 8XC196NT User Manual page 547

8XC196NT USER'S MANUAL
SLP_STAT
SLP_STAT
The master can read the slave port status (SLP_STAT) register to determine the status of the slave.
The slave can read all bits and can write bits 7:3 for general-purpose status information. (The bits are
user-defined flags.) If the master attempts to write to SLP_STAT, it actually writes to SLP_CMD. To
read from this register (rather than P3_REG), the master must first write "1" to the pin selected by
SLP_CON.2.
7
SMO/SF4 SF3
Bit Bit
Number Mnemonic
7 SMO/SF4
6:3 SF3:0
2 CBE
1 IBE
0 OBF
C-52
SF2 SF1
Shared Memory Operation/Status Field Bit 4
In shared memory mode, bit 7 (SMO) indicates whether the bus interface
logic received a read (1) or a write (0). SMO can be read but not written.
In standard slave mode, bit 7 (SF4) is the high bit of the status field.
Status Field
The slave can write to these bits for general-purpose status information.
(The bits are user-defined flags).
Command Buffer Empty
This flag is set after the slave reads SLP_CMD. The flag is cleared and
the command buffer full (CBF) interrupt pending bit (INT_PEND1.0) is
set after the master writes to SLP_CMD.
Input Buffer Empty
This flag is set after the slave reads P3_PIN. The flag is cleared and the
IBF interrupt pending bit (INT_PEND.7) is set after the master writes to
P3_PIN.
Output Buffer Full
This flag is set after the slave writes to P3_REG. The flag is cleared and
the OBE interrupt pending bit (INT_PEND.6) is set after the master
reads P3_REG.
Address:
Reset State:
SF0 CBE
Function
1FF8H
XXH
0
IBE OBF