Intel 8XC196NT User Manual page 256

EPA x _CON (Continued)
x = 0–9
The EPA control (EPA x _CON) registers control the functions of their assigned capture/compare
channels. The registers for EPA0, EPA2, and EPA4–9 are identical. The registers for EPA1 and EPA3
have an additional bit, the remap bit. This added bit (bit 8) requires an additional byte, so EPA1_CON
and EPA3_CON must be addressed as words, while the others can be addressed as bytes.
15
x = 1, 3 —
7
TB
7
x = 0, 2, 4–9 TB
Bit Bit
Number Mnemonic
2 AD
1 ROT
†
These bits apply to the EPA1_CON and EPA3_CON registers only.
Figure 10-10. EPA Control (EPA x _CON) Registers (Continued)
— — —
CE M1 M0
CE M1 M0
A/D Conversion
Allows the EPA to start an A/D conversion that has been previously set up
in the A/D control registers. To use this feature, you must select the EPA
as the conversion source in the AD_CONTROL register.
0 = causes no A/D action
1 = EPA capture or compare event triggers an A/D conversion
Reset Opposite Timer
Controls different functions for capture and compare modes.
In Capture Mode:
0 = causes no action
1 = resets the opposite timer
In Compare Mode:
Selects the timer that is to be reset if the RT bit is set.
0 = selects the reference timer for possible reset
1 = selects the opposite timer for possible reset
The TB bit (bit 7) selects which is the reference timer and which is the
opposite timer.
EVENT PROCESSOR ARRAY (EPA)
Address: See Table 10-2 on
Reset State: F700H ( x = 1 & 3)
00H( x = 0, 2, 4–9)
— —
RE AD ROT
RE AD ROT
Function
page 10-3
8
— RM
0
ON/RT
0
ON/RT
10-23