Intel 8XC196NT User Manual page 465

8XC196NT USER'S MANUAL
Table A-8. Instruction Lengths and Hexadecimal Opcodes (Continued)
Mnemonic
Length
EBR
EJMP
Mnemonic
Length
BR
LJMP
SJMP (Note 3)
TIJMP
Mnemonic
Length
ECALL
Mnemonic
Length
LCALL
RET
SCALL (Note 3)
TRAP
NOTES:
1. Indirect normal and indirect autoincrement share the same opcodes, as do short- and long-indexed
modes. Because word registers always have even addresses, the address can be expressed in the
upper seven bits; the least-significant bit determines the addressing mode. Indirect normal and short-
indexed modes make the second byte of the instruction even (LSB = 0). Indirect autoincrement and
long-indexed modes make the second byte odd (LSB = 1).
2. For indexed instructions, the first column lists instruction lengths as S / L , where S is the short-indexed
instruction length and L is the long-indexed instruction length.
3. For the SCALL and SJMP instructions, the three least-significant bits of the opcode are concatenated
with the eight bits to form an 11-bit, 2's complement offset.
A-56
Jump
Direct Immediate
Opcode Length
— — —
— — —
Direct Immediate
Opcode Length
— — —
— — —
— — —
4 E2 4
Direct Immediate
Opcode Length
— — —
Direct Immediate
Opcode Length
— — —
— — —
— — —
1 F7 —
Extended-indirect
Opcode Length
— 2
— —
Indirect
(Note 1)
Opcode Length
— 2
— —
— —
E2 —
Call
Extended-indirect
Opcode Length Opcode
— —
Indirect
(Note 1)
Opcode Length Opcode
— —
— 1
— —
— —
Extended-
indexed
Opcode Length Opcode
E3 — —
— 4 E6
Indexed
(Notes 1, 2)
Length
Opcode Opcode
S/L
E3 — —
— —/3 E7
— 2/— 20–27
— —/4 E2
Extended-
indexed
Length Opcode
— 4 F1
Indexed
(Note 1)
Length Opcode
— 3 EF
F0 — —
— 2 28–2F
— — —