Intel 8XC196NT User Manual page 467

8XC196NT USER'S MANUAL
Table A-8. Instruction Lengths and Hexadecimal Opcodes (Continued)
Mnemonic
Length
NORML
SHL
SHLB
SHLL
SHR
SHRA
SHRAB
SHRAL
SHRB
SHRL
Mnemonic
Length
CLRC
CLRVT
DI
EI
IDLPD
NOP
RST
SETC
SKIP
Mnemonic
Length
DPTS
EPTS
NOTES:
1. Indirect normal and indirect autoincrement share the same opcodes, as do short- and long-indexed
modes. Because word registers always have even addresses, the address can be expressed in the
upper seven bits; the least-significant bit determines the addressing mode. Indirect normal and short-
indexed modes make the second byte of the instruction even (LSB = 0). Indirect autoincrement and
long-indexed modes make the second byte odd (LSB = 1).
2. For indexed instructions, the first column lists instruction lengths as S / L , where S is the short-indexed
instruction length and L is the long-indexed instruction length.
3. For the SCALL and SJMP instructions, the three least-significant bits of the opcode are concatenated
with the eight bits to form an 11-bit, 2's complement offset.
A-58
Direct Immediate
Opcode Length
3 0F —
3 09 —
3 19 —
3 0D —
3 08 —
3 0A —
3 1A —
3 0E —
3 18 —
3 0C —
Special
Direct Immediate
Opcode Length
1 F8 —
1 FC —
1 FA —
1 FB —
— — 1
1 FD —
1 FF —
1 F9 —
2 00 —
Direct Immediate
Opcode Length
1 EC —
1 ED —
Shift
Indirect
Opcode Length
— —
— —
— —
— —
— —
— —
— —
— —
— —
— —
Indirect
Opcode Length
— —
— —
— —
— —
F6 —
— —
— —
— —
— —
PTS
Indirect
Opcode Length
— —
— —
Indexed
Opcode Length Opcode
— — —
— — —
— — —
— — —
— — —
— — —
— — —
— — —
— — —
— — —
Indexed
Opcode Length Opcode
— — —
— — —
— — —
— — —
— — —
— — —
— — —
— — —
— — —
Indexed
Opcode Length Opcode
— — —
— — —