Intel 8XC196NT User Manual page 257

8XC196NT USER'S MANUAL
EPA x _CON (Continued)
x = 0–9
The EPA control (EPA x _CON) registers control the functions of their assigned capture/compare
channels. The registers for EPA0, EPA2, and EPA4–9 are identical. The registers for EPA1 and EPA3
have an additional bit, the remap bit. This added bit (bit 8) requires an additional byte, so EPA1_CON
and EPA3_CON must be addressed as words, while the others can be addressed as bytes.
15
x = 1, 3 —
7
TB
7
x = 0, 2, 4–9 TB
Bit Bit
Number Mnemonic
0 ON/RT
†
These bits apply to the EPA1_CON and EPA3_CON registers only.
Figure 10-10. EPA Control (EPA x _CON) Registers (Continued)
10-24
— — —
CE M1 M0
CE M1 M0
Overwrite New/Reset Timer
The ON/RT bit functions as overwrite new in capture mode and reset
timer in compare mode.
In Capture Mode (ON):
An overrun error is generated when an input capture occurs while the
event-time register (EPA x _TIME) and its buffer are both full. When an
overrun occurs, the ON bit determines whether old data is overwritten or
new data is ignored:
0 = ignores new data
1 = overwrites old data in the buffer
In Compare Mode (RT):
0 = disables the reset function
1 = resets the ROT-selected timer
Address: See Table 10-2 on
Reset State: F700H ( x = 1 & 3)
00H( x = 0, 2, 4–9)
— —
RE AD ROT
RE AD ROT
Function
page 10-3
8
— RM
0
ON/RT
0
ON/RT