Intel 8XC196NT User Manual page 466

Table A-8. Instruction Lengths and Hexadecimal Opcodes (Continued)
Mnemonic
Length
DJNZ
DJNZW
JBC
JBS
JC
JE
JGE
JGT
JH
JLE
JLT
JNC
JNE
JNH
JNST
JNV
JNVT
JST
JV
JVT
NOTES:
1. Indirect normal and indirect autoincrement share the same opcodes, as do short- and long-indexed
modes. Because word registers always have even addresses, the address can be expressed in the
upper seven bits; the least-significant bit determines the addressing mode. Indirect normal and short-
indexed modes make the second byte of the instruction even (LSB = 0). Indirect autoincrement and
long-indexed modes make the second byte odd (LSB = 1).
2. For indexed instructions, the first column lists instruction lengths as S / L , where S is the short-indexed
instruction length and L is the long-indexed instruction length.
3. For the SCALL and SJMP instructions, the three least-significant bits of the opcode are concatenated
with the eight bits to form an 11-bit, 2's complement offset.
Conditional Jump
Direct Immediate
Opcode Length
— — —
— — —
— — —
— — —
— — —
— — —
— — —
— — —
— — —
— — —
— — —
— — —
— — —
— — —
— — —
— — —
— — —
— — —
— — —
— — —
INSTRUCTION SET REFERENCE
Indirect
Opcode Length Opcode
— — —
— — —
— — —
— — —
— — —
— — —
— — —
— — —
— — —
— — —
— — —
— — —
— — —
— — —
— — —
— — —
— — —
— — —
— — —
— — —
Indexed
(Notes 1, 2)
Length
Opcode
S/L
3/— E0
3/— E1
3/— 30–37
3/— 38–3F
2/— DB
2/— DF
2/— D6
2/— D2
2/— D9
2/— DA
2/— DE
2/— D3
2/— D7
2/— D1
2/— D0
2/— D5
2/— D4
2/— D8
2/— DD
2/— DC
A-57