Bidirectional Ports 3 And 4 (Address/Data Bus) Operation - Intel 8XC196NT User Manual

Special-function
Port Pins
AD7:0
P3.7:0 PBUS7:0
SLP7:0
AD15:8
P4.7:0
PBUS15:8
Table 6-12. Ports 3 and 4 Control and Status Registers
Mnemonic Address
P3_PIN 1FFEH
P4_PIN 1FFFH
P3_REG 1FFCH
P4_REG 1FFDH
P34_DRV 1FF4H
6.4.1

Bidirectional Ports 3 and 4 (Address/Data Bus) Operation

Figure 6-3 shows the ports 3 and 4 logic. During reset, the active-low level of RESET# turns off
Q1 and Q2 and turns on transistor Q4, which weakly holds the pin high. (Q4 can source approx-
imately –10 µΑ at V
CC
vides ESD protection for the pin.
During normal operation, the device controls the port through BUS CONTROL SELECT, an in-
ternal control signal. When the device needs to access external memory, it clears BUS CON-
TROL SELECT, selecting ADDRESS/DATA as the input to the multiplexer. ADDRESS/DATA
then drives Q1 and Q2 as complementary outputs. (Q1 can source at least –3 mA at V
volts; Q2 can sink at least 3 mA at 0.45 volts. Consult the datasheet for exact specifications.)
Table 6-11. Ports 3 and 4 Pins
Special-function
Signal(s)
Port x Input
Each bit of P x _PIN reflects the current state of the corresponding pin,
regardless of the pin configuration.
Port x Data Output
Each bit of P x _REG contains data to be driven out by the corresponding
pin.
When the device requires access to external memory, it takes control of
the port and drives the address/data bit onto the pin. The address/data
bit replaces your output during this time. When the external access is
completed, the device restores your data onto the pin.
Ports 3/4 Driver Enable Register
Bits 7 and 6 of the P34_DRV register control whether ports 3 and 4,
respectively, are configured as complementary or open-drain. Setting a
bit configures a port as complementary; clearing a bit configures a port
as open-drain. These bits affect port operation only in I/O mode.
– 1.0 volts; consult the datasheet for exact specifications.) Resistor R1 pro-
Signal Type
I/O Address/data bus, low byte
I/O Programming bus, low byte
I/O Slave port
I/O Address/data bus, high byte
I/O Programming bus, high byte
Description
I/O PORTS
Associated Peripheral
CC
–0.7
6-15