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8XC196NT USER'S MANUAL
Figure
7-5
Serial Port Frames in Mode 2 and 3.............................................................................7-7
7-6
Serial Port Control (SP_CON) Register........................................................................7-9
7-7
Serial Port Baud Rate (SP_BAUD) Register ..............................................................7-10
7-8
Serial Port Status (SP_STATUS) Register.................................................................7-12
8-1
SSIO Block Diagram ....................................................................................................8-1
8-2
SSIO Operating Modes ................................................................................................8-4
8-3
SSIO Transmit/Receive Timings ..................................................................................8-6
8-4
SSIO Handshaking Flow Diagram................................................................................8-7
8-5
Synchronous Serial Port Baud (SSIO_BAUD) Register .............................................8-10
8-6
Synchronous Serial Control x (SSIO x _CON) Registers .............................................8-11
8-7
Variable-width MSB in SSIO Transmissions ..............................................................8-14
9-1
DPRAM vs Slave-port Solution.....................................................................................9-2
9-2
Slave Port Block Diagram.............................................................................................9-3
9-3
Master/Slave Hardware Connections ...........................................................................9-7
9-4
Standard Slave Mode Timings (Demultiplexed Bus) ..................................................9-10
9-5
Standard or Shared Memory Mode Timings (Multiplexed Bus)..................................9-13
9-6
Slave Port Control (SLP_CON) Register....................................................................9-15
9-7
Slave Port Status (SLP_STAT) Register ....................................................................9-17
10-1
EPA Block Diagram ....................................................................................................10-2
10-2
EPA Timer/Counters ..................................................................................................10-6
10-3
Quadrature Mode Interface ........................................................................................10-8
10-4
Quadrature Mode Timing and Count ..........................................................................10-9
10-5
A Single EPA Capture/Compare Channel ................................................................10-10
10-6
EPA Simplified Input-capture Structure ....................................................................10-11
10-7
Valid EPA Input Events ............................................................................................10-12
10-8
Timer 1 Control (T1CONTROL) Register .................................................................10-18
10-9
Timer 2 Control (T2CONTROL) Register .................................................................10-19
10-10
EPA Control (EPA x _CON) Registers .......................................................................10-21
EPA Compare Control (COMP x _CON) Registers....................................................10-25
10-11
10-12
EPA Interrupt Mask (EPA_MASK) Register .............................................................10-27
10-13
EPA Interrupt Mask 1 (EPA_MASK1) Register ........................................................10-27
10-14
EPA Interrupt Pending (EPA_PEND) Register.........................................................10-28
10-15
EPA Interrupt Pending 1 (EPA_PEND1) Register....................................................10-28
10-16
EPA Interrupt Priority Vector (EPAIPV) Register......................................................10-30
11-1
A/D Converter Block Diagram ....................................................................................11-1
11-2
A/D Test (AD_TEST) Register....................................................................................11-5
11-3
A/D Result (AD_RESULT) Register — Write Format .................................................11-6
11-4
A/D Time (AD_TIME) Register ...................................................................................11-7
11-5
A/D Command (AD_COMMAND) Register ................................................................11-8
11-6
A/D Result (AD_RESULT) Register — Read Format...............................................11-10
11-7
Idealized A/D Sampling Circuitry ..............................................................................11-11
11-8
Suggested A/D Input Circuit .....................................................................................11-13
11-9
Ideal A/D Conversion Characteristic.........................................................................11-16
11-10
Actual and Ideal A/D Conversion Characteristics.....................................................11-17
xiv
FIGURES
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