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Name
Type
RESET#
I/O
RXD
I/O
SC1:0
I/O
SD1:0
I/O
SLP7:0
I/O
SLPALE
I
SLPCS#
I
SLPINT
O
SLPRD#
I
SLPWR#
I
Table B-4. Signal Descriptions (Continued)
Reset
A level-sensitive reset input to and open-drain system reset output from the
microcontroller. Either a falling edge on RESET# or an internal reset turns on a
pull-down transistor connected to the RESET# pin for 16 state times. In the
powerdown and idle modes, asserting RESET# causes the chip to reset and
return to normal operating mode. The microcontroller resets to FF2080H in
internal ROM or F2080H in external memory.
Receive Serial Data
In modes 1, 2, and 3, RXD receives serial port input data. In mode 0, it
functions as either an input or an open-drain output for data.
RXD is multiplexed with P2.1 and PALE#.
Clock Pins for SSIO0 and 1
For handshaking mode, configure SC1:0 as open-drain outputs.
This pin carries a signal only during receptions and transmissions. When the
SSIO port is idle, the pin remains either high (with handshaking) or low (without
handshaking).
SC0 is multiplexed with P6.4, and SC1 is multiplexed with P6.6.
Data Pins for SSIO0 and 1
SD0 is multiplexed with P6.5, and SD1 is multiplexed with P6.7.
Slave Port Address/Data bus
Slave port address/data bus in multiplexed mode and slave port data bus in
demultiplexed mode. In multiplexed mode, SLP1 is the source of the internal
control signal, SLP_ADDR.
SLP7:0 are multiplexed with AD7:0, P3.7:0, and PBUS.7:0.
Slave Port Address Latch Enable
Functions as either a latch enable input to latch the value on SLP1 (with a
multiplexed address/data bus) or as the source of the internal control signal,
SLP_ADDR (with a demultiplexed address/data bus).
SLPALE is multiplexed with P5.0, ADV#, and ALE.
Slave Port Chip Select
SLPCS# must be held low to enable slave port operation.
SLPCS# is multiplexed with P5.1 and INST.
Slave Port Interrupt
This active-high slave port output signal can be used to interrupt the master
processor.
SLPINT is multiplexed with P5.4 and a special test-mode-entry pin . See P5.7:0
for special considerations.
Slave Port Read Control Input
This active-low signal is an input to the slave. Data from the P3_REG or
SLP_STAT register is valid after the falling edge of SLPRD#.
SLPRD# is multiplexed with P5.3 and RD#.
Slave Port Write Control Input
This active-low signal is an input to the slave. The rising edge of SLPWR#
latches data on port 3 into the P3_PIN or SLP_CMD register.
SLPWR# is multiplexed with P5.2, WR#, and WRL#.
SIGNAL DESCRIPTIONS
Description
B-11
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