Bidirectional Port Considerations - Intel 8XC196NT User Manual

Table 6-10. Port Pin States After Reset and After Example Code Execution
Action or Code
Reset
LDB P x _DIR, #00011111B
LDB P x _MODE, #00000000B
LDB P x _REG, #10010011B
†
wk1 = weakly pulled high, HZ1 = high impedance (actually a "1" with an external pull-up).
6.3.4

Bidirectional Port Considerations

This section outlines special considerations for using the pins of these ports.
Port 1
Port 2
P2.2/EXTINT
P2.5/HOLD#
Px.7 Px.6
wk1 wk1
1 1
1 1
1 0
After reset, your software must configure the device to match the
external system. This is accomplished by writing appropriate config-
uration data into P1_MODE. Writing to P1_MODE not only
configures the pins but also turns off the transistor that weakly holds
the pins high (Q4 in Figure 6-2 on page 6-7). For this reason, even if
port 1 is to be used as it is configured at reset, you should still write
data into P1_MODE.
After reset, your software must configure the device to match the
external system. This is accomplished by writing appropriate config-
uration data into P2_MODE. Writing to P2_MODE not only
configures the pins but also turns off the transistor that weakly holds
the pins high (Q4 in Figure 6-2 on page 6-7). For this reason, even if
port 2 is to be used as it is configured at reset, you should still write
data into P2_MODE.
Writing to P2_MODE.2 sets the EXTINT interrupt pending bit. After
configuring the port pins, clear the interrupt pending register before
enabling interrupts. See "Design Considerations for External
Interrupt Inputs" on page 6-14.
If P2.5 is configured as a standard I/O port pin, the device does not
recognize signals on this pin as HOLD#. Instead, the bus controller
receives an internal HOLD signal. This enables the device to access
the external bus while it is performing I/O at P2.5.
Resulting Pin States
Px.5 Px.4 Px.3
wk1 wk1 wk1
1 wk1 wk1
1 HZ1 HZ1
0 HZ1 0
I/O PORTS
†
Px.2 Px.1 Px.0
wk1 wk1 wk1
wk1 wk1 wk1
HZ1 HZ1 HZ1
0 HZ1 HZ1
6-11