Eport Operation - Intel 8XC196NT User Manual

Table 6-15. EPORT Control and Status Registers (Continued)
Mnemonic Address
EP_MODE 1FE1H
EP_PIN 1FE7H
EP_REG 1FE5H
6.5.1

EPORT Operation

As Figure 6-4 shows, each EPORT pin serves either as I/O or as an address line, as selected by
the I/O multiplexer. This multiplexer is controlled by the EP_MODE register. If EP_MODE is
clear (I/O mode), the pin serves as I/O until EP_MODE is changed.
EPORT Mode
Each bit of EP_MODE controls whether the corresponding pin
functions as a standard I/O port pin or as an extended-address
signal. Setting a bit configures a pin as an extended-address signal;
clearing a bit configures a pin as a standard I/O port pin.
EPORT Pin State
Each bit of EP_PIN reflects the current state of the corresponding
pin, regardless of the pin configuration.
EPORT Data Output
Each bit of EP_REG contains data to be driven out by the corre-
sponding pin. When a pin is configured as standard I/O
(EP_MODE. x =0), the result of a CPU write to EP_REG is
immediately visible on the pin.
During nonextended data accesses, EP_REG contains the value of
the memory page that is to be accessed. For compatibility with
software tools, clear the EP_REG bit for any EPORT pin that is
configured as an extended-address signal (EP_MODE. x set).
Description
I/O PORTS
6-19