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Symbol
The 8XC196NT Meets These Specifications (Continued)
T
CLKOUT Falling to ALE/ADV# Rising
CLLH
Use to derive other timings.
T
CLKOUT Low to ALE/ADV# Low (modes 1 and 2 only)
CLLL
Time between CLKOUT going low and ALE/ADV# going low. Use to derive other timings.
T
ALE Cycle Time
LHLH
Minimum time between ALE pulses.
T
ALE/ADV# High Period
LHLL
Use this specification when designing the external latch.
T
Address Hold after ALE/ADV# Low
LLAX
Length of time address is valid after ALE/ADV# falls. Use this specification when designing the
external latch.
T
ALE/ADV# Falling to CLKOUT Rising
LLCH
Use to derive other timings.
T
ALE/ADV# Low to RD# Low
LLRL
Length of time after ALE/ADV# falls before RD# is asserted. Could be needed to ensure that
proper memory decoding takes place before a device is enabled.
T
ALE/ADV# Low to WR# Low
LLWL
Length of time after ALE/ADV# falls before WR# is asserted. Could be needed to ensure that
proper memory decoding takes place before a device is enabled.
T
Data Valid to WR# High
QVWH
Time between data being valid on the bus and WR# going inactive.
T
AD15:8 Hold after RD# High
RHAX
Minimum time the high byte of the address in 8-bit mode will be valid after RD# inactive.
T
BHE#, INST Hold after RD# High
RHBX
Minimum time these signals will be valid after RD# inactive.
T
RD# High to ALE/ADV# Asserted
RHLH
Time between RD# going inactive and the next ALE/ADV#. Useful in calculating time between
inactive and next address valid.
T
RD# Low to Address Float
RLAZ
Used to calculate when the 8XC196NT stops driving address on the bus.
T
RD# Low to RD# High
RLRH
RD# pulse width.
T
AD15:8 Hold after WR# High
WHAX
Minimum time the high byte of the address in 8-bit mode will be valid after WR# inactive.
T
BHE#, INST Hold after WR# High
WHBX
Minimum time these signals will be valid after WR# inactive.
Table 14-9. AC Timing Definitions (Continued)
INTERFACING WITH EXTERNAL MEMORY
Definition
14-41
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