Intel 8XC196NT User Manual page 261

8XC196NT USER'S MANUAL
The EPA0–EPA3 pending bits are located in INT_PEND (Figure 5-7 on page 5-17). The pending
bits for the multiplexed interrupts (those that share EPAx) are located in EPA_PEND (Figure
10-14) and EPA_PEND1 (Figure 10-15). If an interrupt is masked, software can still poll the in-
terrupt pending registers to determine whether an event has occurred.
EPA_PEND
When hardware detects a pending EPA x interrupt, it sets the corresponding bit in the EPA interrupt
pending (EPA_PEND or EPA_PEND1) registers. The EPAIPV register contains a number that
identifies the highest priority, active, multiplexed interrupt source. When EPAIPV is read, the EPA
interrupt pending bit associated with the EPAIPV priority value is cleared.
15
EPA4 EPA5
7
OVR2 OVR3
Bit
Number
15:10 Any set bit indicates that the corresponding EPA x interrupt source is pending. The bit is
cleared when the EPA interrupt priority vector register (EPAIPV) is read.
Figure 10-14. EPA Interrupt Pending (EPA_PEND) Register
EPA_PEND1
When hardware detects a pending EPA x interrupt, it sets the corresponding bit in EPA interrupt
pending (EPA_PEND or EPA_PEND1) registers. The EPAIPV register contains a number that
identifies the highest priority, active, multiplexed interrupt source. When EPAIPV is read, the EPA
interrupt pending bit associated with the EPAIPV priority value is cleared.
7
— —
Bit
Number
7:4 Reserved; always write as zeros.
3:0 Any set bit indicates that the corresponding EPA x interrupt source is pending. The bit is
cleared when the EPA interrupt priority vector register (EPAIPV) is read.
Figure 10-15. EPA Interrupt Pending 1 (EPA_PEND1) Register
10-28
EPA6 EPA7
OVR4 OVR5
Function
— —
Function
Reset State:
EPA8 EPA9
OVR6 OVR7
Reset State:
COMP0 COMP1 OVRTM1
Address: 1FA2H
0000H
8
OVR0 OVR1
0
OVR8 OVR9
Address: 1FA6H
00H
0
OVRTM2