Intel 8XC196NT User Manual page 238

Table 10-2. EPA Control and Status Registers (Continued)
Mnemonic Address
P1_REG 1FD4H
P6_REG 1FD5H
T1CONTROL 1F98H
T2CONTROL 1F9CH
TIMER1 1F9AH
TIMER2 1F9EH
EVENT PROCESSOR ARRAY (EPA)
Port x Data Output
For an input, set the corresponding P x _REG bit.
For an output, write the data to be driven out by each pin to the
corresponding bit of P x _REG. When a pin is configured as
standard I/O (P x _MODE. x =0), the result of a CPU write to
P x _REG is immediately visible on the pin. When a pin is
configured as a special-function signal (P x _MODE. x =1), the
associated on-chip peripheral or off-chip component controls the
pin. The CPU can still write to P x _REG, but the pin is unaffected
until it is switched back to its standard I/O function.
This feature allows software to configure a pin as standard I/O
(clear P x _MODE. x ), initialize or overwrite the pin value, then
configure the pin as a special-function signal (set P x _MODE. x ). In
this way, initialization, fault recovery, exception handling, etc., can
be done without changing the operation of the associated
peripheral.
Timer 1 Control
This register enables/disables timer 1, controls whether it counts
up or down, selects the clock source and direction, and
determines the clock prescaler setting.
Timer 2 Control
This register enables/disables timer 2, controls whether it counts
up or down, selects the clock source and direction, and
determines the clock prescaler setting.
Timer 1 Value
This register contains the current value of timer 1.
Timer 2 Value
This register contains the current value of timer 2.
Description
10-5