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8XC196NT USER'S MANUAL
Setup and hold timings must be met when using the READY signal to insert wait states into a bus
cycle (see Table 14-3 and Figure 14-8). Because a decoded, valid address is used to generate the
READY signal, the setup time is specified relative to the address being valid. This specification,
T
, indicates how much time one has to decode the address and assert READY after the ad-
AVYV
dress is valid. The READY signal must be held valid until the T
Typically, this is a minimum of 0 ns from the time CLKOUT goes low. Do not exceed the maxi-
mum T
specification or additional (unwanted) wait states might be added. In all cases, refer
CLYX
to the data sheets for the current specifications for T
.
Symbol
T
READY Hold after CLKOUT Low
CLYX
Minimum hold time is typically 0 ns. If maximum specification is exceeded, additional wait
states will occur.
T
Address Valid to READY Setup
AVYV
Maximum time the memory system has to assert READY after the device outputs the address
to guarantee that at least one wait state will occur.
14-18
Table 14-3. READY Signal Timing Definitions
timing specification is met.
CLYX
and T
.
AVYV
CLYX
Definition
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