Overview Of The Instruction Set - Intel 8XC196NT User Manual

This section provides an overview of the instruction set of the MCS
fers guidelines for program development. For detailed information about specific instructions,
see Appendix A.
3.1 OVERVIEW OF THE
The instruction set supports a variety of operand types likely to be useful in control applications
(see Table 3-1).
The operand-type variables are shown in all capitals to avoid confusion. For
example, a BYTE is an unsigned 8-bit variable in an instruction, while a byte is
any 8-bit unit of data (either signed or unsigned).
No. of
Operand Type
Bits
BIT
BYTE
SHORT-INTEGER
WORD
INTEGER
DOUBLE-WORD
(Note 1)
LONG-INTEGER
(Note 1)
QUAD-WORD
(Note 3)
NOTES:
1. The 32-bit variables are supported only as the operand in shift operations, as the dividend in 32-by-
16 divide operations, and as the product of 16-by-16 multiply operations.
2. For consistency with third-party software, you should adopt the C programming conventions for
addressing 32-bit operands. For more information, refer to page 3-11.
3. QUAD-WORD variables are supported only as the operand for the EBMOVI instruction.
PROGRAMMING CONSIDERATIONS
INSTRUCTION SET
Table 3-1. Operand Type Definitions
Signed Possible Values
1 No True or False
8 No 0 through 2
7
8 Yes –2 through +2
(–128 through +127)
16 No 0 through 2
(0 through 65,535)
15
16 Yes –2 through +2
(–32,768 through +32,767)
32 No 0 through 2
(0 through 4,294,967,295)
31
32 Yes –2 through +2
(–2,147,483,648 through
+2,147,483,647)
64 No 0 through 2
®
NOTE
8
–1 (0 through 255)
7
–1
16
–1
15
–1
32
–1
31
–1
64
–1
CHAPTER 3
96 microcontrollers and of-
Addressing
Restrictions
As components of bytes
None
None
Even byte address
Even byte address
An address in the lower
register file that is evenly
divisible by four (Note 2)
An address in the lower
register file that is evenly
divisible by four (Note 2)
An address in the lower
register file that is evenly
divisible by eight
3-1