Intel 8XC196NT User Manual page 546

SLP_CON
The slave port control (SLP_CON) register is used to configure the slave port. Only the slave can
access the register.
7
— —
Bit Bit
Number Mnemonic
7:5 —
4 SME
3 SLP
2 SLPL
1 IBEMSK
0 OBFMSK
— SME
Reserved. These bits are undefined; for compatibility with future devices,
do not modify these bits.
Shared Memory Enable
Enables slave port shared memory mode.
0 = standard slave mode
1 = shared memory mode
Slave Port Enable
This bit enables or disables the slave port.
0 = disables the slave port and clears the command buffer empty (CBE),
input buffer empty (IBE), and output buffer full (OBF) flags in the
SLP_STAT register.
1 = enables the slave port
Slave Port Latch
In standard slave mode only, this bit determines the source of the
internal control signal, SLP_ADDR. When SLP_ADDR is held high, the
master can write to the SLP_CMD register and read from the SLP_STAT
register. When SLP_ADDR is held low, the master can write to the
P3_PIN register and read from the P3_REG register.
0 = SLPALE (P5.0) via master's A1 signal. Use with demultiplexed bus.
1 = SLP1 (P3.1) via master's AD1 signal. Use with multiplexed bus.
In shared memory mode, this bit has no function.
Input Buffer Empty Mask
Controls whether the IBE flag (in SLP_STAT) asserts the SLPINT signal.
In shared memory mode, this bit has no effect on the SLPINT signal.
Output Buffer Full Mask
Controls whether the OBF flag (in SLP_STAT) asserts the SLPINT
signal.
In shared memory mode, this bit has no effect on the SLPINT signal.
Address:
Reset State:
SLP SLPL IBEMSK
Function
REGISTERS
SLP_CON
1FFBH
X0H
0
OBFMSK
C-51