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8XC196NT USER'S MANUAL
The 64K×8 RAM stores far data at addresses 10000–1FFFFH; code could also execute from this
RAM. The top 64K×8 flash memory stores near data at addresses 00600–01EFFH and 02000–
0FFFH. The bottom 64K×8 flash memory stores code, special-purpose memory, and far data at
addresses F0000–FFFFFH. Code execution begins from page FFH; the address decoding logic
selects the bottom 64K×8 flash memory (which could be considered page 0FH, 07H, or 03H).
The bus-timing mode must be either mode 0 or mode 3 because only one address latch is used.
(See "Bus Timing Modes" on page 14-34.) Table 4-14 lists the memory addresses for this exam-
ple. This memory map assumes that the IRAM bit (IRAM_CON.6) is set, so accesses to FF0400–
FF05FFH are directed to the external flash memory.
Table 4-17. Memory Map for the System in Figure 4-12
Address
FFFFFF
External code, special-purpose memory, and far data
FF0100
(implemented by bottom 64K×8 external flash)
FF00FF
Reserved
FF0000
0FFFFF
Unimplemented
020000
01FFFF
External code and far data (implemented by 64K×8 external RAM)
010000
00FFFF
Near data (implemented by top 64K×8 external flash)
002000
001FFF
Memory-mapped SFRs
001FE0
001FDF
Peripheral SFRs
001F00
001EFF
Near data (implemented by top 64K×8 external flash)
000600
0005FF
Internal code and data RAM
000400
0003FF
Upper register file (general-purpose register RAM)
000100
0000FF
Lower register file (general-purpose register RAM, stack pointer, and CPU SFRs)
000000
4-36
Description
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