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OTPROM
p-channel FET
p-type material
PC
PCCBs
PIC
prioritized interrupt
program memory
protected instruction
PSW
PTS
One-time-programmable read-only memory. Similar
to EPROM, but it comes in an unwindowed package
and cannot be erased.
A field-effect transistor with a p-type conducting
path.
Semiconductor material with introduced impurities
(doping) causing it to have an excess of positively
charged carriers.
Program counter.
Programming chip configuration bytes, which are
loaded into the chip configuration registers (CCRs)
when the device is entering programming modes;
otherwise, the CCBs are used.
Programmable interrupt controller. The module
responsible for handling interrupts that are to be
serviced by interrupt service routines that you
provide. Also called simply the interrupt controller.
Any maskable interrupt or nonmaskable NMI. Two of
the nonmaskable interrupts (unimplemented opcode
and software trap) are not prioritized; they vector
directly to the interrupt service routine when
executed.
A partition of memory where instructions can be
stored for fetching and execution.
An instruction that prevents an interrupt from being
acknowledged until after the next instruction
executes. The protected instructions are DI, EI, DPTS,
EPTS, POPA, POPF, PUSHA, and PUSHF.
Program status word. The high byte of the PSW is the
status byte, which contains one bit that globally
enables or disables servicing of all maskable
interrupts, one bit that enables or disables the PTS,
and six Boolean flags that reflect the state of the
current program. The low byte of the PSW is the
INT_MASK register. A push or pop instruction saves
or restores both bytes (PSW + INT_MASK).
Peripheral
transaction server.
hardware interrupt processor.
GLOSSARY
The
microcoded
Glossary-7
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