Intel 8XC196NT User Manual page 572

interrupt controller
interrupt latency
interrupt service routine
interrupt vector
ISR
linearity errors
LONG-INTEGER
LSB
maskable interrupts
monotonic
The module responsible for handling interrupts that
are to be serviced by interrupt service routines that
you provide. Also called the programmable interrupt
controller (PIC).
The total delay between the time that an interrupt is
generated (not acknowledged) and the time that the
device begins executing the interrupt service routine
or PTS routine.
A software routine that you provide to service a
standard interrupt. See also PTS routine.
A location in special-purpose memory that holds the
starting address of an interrupt service routine.
See interrupt service routine.
See differential nonlinearity and nonlinearity.
A 32-bit, signed variable with values from –2
31
through +2 –1.
1) Least-significant bit of a byte or least-significant
byte of a word.
2) In an A/D converter, the reference voltage divided
n
by 2 , where n is the number of bits to be converted.
For a 10-bit converter with a reference voltage of 5.12
volts, one LSB is equal to 5.0 millivolts (5.12 ÷ 2
All interrupts except
software trap, and NMI. Maskable interrupts can be
disabled (masked) by the individual mask bits in the
interrupt mask registers, and their servicing can be
disabled by the global interrupt enable bit. Each
maskable interrupt can be assigned to the PTS for
processing.
The property of successive approximation converters
which guarantees that increasing input voltages
produce adjacent codes of increasing value, and that
decreasing input voltages produce adjacent codes of
decreasing value. (In other words, a converter is
monotonic if every code change represents an input
voltage change in the same direction.) Large differ-
ential nonlinearity errors can cause the converter to
exhibit nonmonotonic behavior.
GLOSSARY
10
unimplemented opcode,
Glossary-5
31
)