Table of Contents
Advertisement
SERIAL I/O (SIO) PORT
During a reception, the RI flag in SP_STATUS is set after the stop bit is sampled. The RI pending
bit in the interrupt pending register is set immediately before the RI flag is set. During a transmis-
sion, the TI flag is set immediately after the end of the last (eighth) data bit is transmitted. The TI
pending bit in the interrupt pending register is generated when the TI flag in SP_STATUS is set.
TXD
RXD (OUT)
D0
D1
D2
D3
D4
D5
D6
D7
RXD (IN)
D0
D1
D2
D3
D4
D5
D6
D7
Expanded:
XTAL1
TXD
RXD (OUT)
D0
D1
D2
RXD (IN)
D0
D1
A0109-02
Figure 7-3. Mode 0 Timing
7.3.2
Asynchronous Modes (Modes 1, 2, and 3)
Modes 1, 2, and 3 are full-duplex serial transmit/receive modes, meaning that they can transmit
and receive data simultaneously. Mode 1 is the standard 8-bit, asynchronous mode used for nor-
mal serial communications. Modes 2 and 3 are 9-bit asynchronous modes typically used for in-
terprocessor communications (see "Multiprocessor Communications" on page 7-7). In mode 2,
the serial port sets an interrupt pending bit only if the ninth data bit is set. In mode 3, the serial
port always sets an interrupt pending bit upon completion of a data transmission or reception.
When the serial port is configured for mode 1, 2, or 3, writing to SBUF_TX causes the serial port
to start transmitting data. New data placed in SBUF_TX is transmitted only after the stop bit of
the previous data has been sent. A falling edge on the RXD input causes the serial port to begin
receiving data if RXD is enabled. Disabling RXD stops a reception in progress and inhibits fur-
ther receptions. (See "Programming the Control Register" on page 7-8.)
7.3.2.1
Mode 1
Mode 1 is the standard asynchronous communications mode. The data frame used in this mode
(Figure 7-4) consists of ten bits: a start bit (0), eight data bits (LSB first), and a stop bit (1). If
parity is enabled, a parity bit is sent instead of the eighth data bit, and parity is checked on recep-
tion.
7-5
Advertisement
Table of Contents
