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13.4.2 Entering Powerdown Mode
Before entering powerdown, complete the following tasks:
•
Complete all serial port transmissions or receptions. Otherwise, when the device exits
powerdown, the serial port activity will continue where it left off and incorrect data may be
transmitted or received.
•
Complete all analog conversions. If powerdown occurs during the conversion, the result
will be incorrect.
•
If the watchdog timer (WDT) is enabled, clear the WATCHDOG register just before issuing
the powerdown instruction. This ensures that the device can exit powerdown cleanly.
Otherwise, the WDT could reset the device before the oscillator stabilizes. (The WDT
cannot reset the device during powerdown because the clock is stopped.)
•
Put all other peripherals into an inactive state.
•
To allow other devices to control the bus while the microcontroller is in powerdown, assert
HLDA#. Do this only if the routines for entering and exiting powerdown do not require
access to external memory.
After completing these tasks, execute the IDLPD #2 instruction to enter powerdown mode.
To prevent an accidental return to full power, hold the external interrupt pin
(EXTINT) low while the device is in powerdown mode.
13.4.3 Exiting Powerdown Mode
The device will exit powerdown mode when one of the following events occurs:
•
an external device drives the V
•
a hardware reset is generated, or
•
a transition occurs on the external interrupt pin.
13.4.3.1
Driving the V
If the design uses an external clock input signal rather than the on-chip oscillator, the fastest way
to exit powerdown mode is to drive the V
using an external clock input because the internal CPU and peripheral clocks will be enabled, but
the internal oscillator will not.
NOTE
pin low for at least 50 ns,
PP
Pin Low
PP
pin low for at least 50 ns. Use this method only when
PP
SPECIAL OPERATING MODES
13-5
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