Eport Status During Instruction Execution; Design Considerations - Intel 8XC196NT User Manual

8XC196NT USER'S MANUAL
6.5.3.3

EPORT Status During Instruction Execution

When using the EPORT to address memory outside page 00H, keep these points in mind:
1. During extended accesses, the upper four bits of the address (lower four bits of the EPC)
are sent to the EPORT. EPORT pins configured for the extended-address function
(EP_MODE.x set) output this address.
2. During nonextended accesses, EPORT pins configured for the extended-address function
(EP_MODE.x set) output the value contained in EP_REG.
3. Any nonextended or direct instruction that accesses the register file or the windowable
SFRs is always directed internally to these areas, regardless of the page from which code
is executing. This effectively maps the register file and windowable SFRs into every page.
Extended instructions can access the "mapped over" areas of each page, as shown in the
following code example.
EST 1CH, 01001CH[0]
6.5.3.4

Design Considerations

At the end of EPORT bus activity and during periods of internal bus activity, EPORT pins con-
tinue to drive the last data address that was output. If these lines are being used to enable external
memory, that memory will remain enabled until a different page is accessed.
During the CCB fetch, all EPORT lines are strongly driven high. Designers should ensure that
this does not conflict with external systems that are outputting signals to the EPORT.
When EPORT pins are floated during idle, powerdown, or hold, the external system must provide
circuitry to prevent CMOS inputs on external devices from floating. During powerdown, the
EPORT input buffers on pins configured for their extended-address function are disconnected
from the pins, so a floating pin will not cause increased power consumption.
Open-drain outputs require an external pull-up resistor. Inputs must be driven or pulled high or
low; they must not be allowed to float.
6-26
;reg 1CH stored at memory location 01001CH