Intel 8XC196NT User Manual page 162

P5.4/SLPINT
P5.5/BHE#/WRH#
P5.6/READY
P5.7/BUSWIDTH
Port 6
P6.7:4
This pin is weakly held high until your software writes to
P5_MODE. P5.4/SLPINT is one of the enable pins for Intel-reserved
test modes. Because a low input during reset could cause the device
to enter a reserved test mode, exercise caution if you use this pin for
input. Be certain that your system meets the V
in the datasheet) during reset to prevent inadvertent entry into ONCE
mode or a test mode.
This pin is weakly held high until the CCB fetch is completed. At
that time, the state of this pin depends on the value of the BW0 bit of
the CCRs. If BW0 is clear, the pin remains weakly held high until
your software writes to P5_MODE. If BW0 is set, BHE# is activated
as a system control pin and the pin becomes a true complementary
output.
This pin remains weakly held high until the CCB fetch is completed.
At that time, the state of this pin depends on the value of the IRC0–
IRC2 bits of the CCRs. If IRC0–IRC2 are all set (111B), READY is
activated as a system control pin. This prevents the insertion of
infinite wait states upon the first access to external memory. For any
other values of IRC0–IRC2, the pin is configured as I/O upon reset.
NOTE: If IRC0–IRC2 of the CCB are all set (activating READY as
a system control pin) and P5_MODE.6 is cleared (config-
uring the pin as I/O), an external memory access may cause
the processor to lock up.
This pin remains weakly held high until your software writes config-
uration data into P5_MODE.
After reset, your software must configure the device to match the
external system. This is accomplished by writing appropriate config-
uration data into P6_MODE. Writing to P6_MODE not only
configures the pins but also turns off the transistor that weakly holds
the pins high (Q4 in Figure 6-2 on page 6-7). For this reason, even if
port 6 is to be used as it is configured at reset, you should still write
data into P6_MODE.
A value written to any of the upper four bits of P6_REG (bits 7:4) is
held in a buffer until the corresponding P6_MODE bit is cleared, at
which time the value is loaded into the P6_REG bit. A value read
from a P6_REG bit is the value currently in the register, not the value
in the buffer. Therefore, any change to a P6_REG bit can be read
only after the corresponding P6_MODE bit is cleared.
I/O PORTS
specification (listed
IH
6-13