Bidirectional Port Operation - Intel 8XC196NT User Manual

ter is a status register that returns the logic level present on the pins; it can only be read. The
registers for the standard ports are byte-addressable and can be windowed. The port 5 registers
must be accessed using 16-bit addressing and cannot be windowed. "Bidirectional Port Consid-
erations" on page 6-11 discusses special considerations for reading P2_REG.7 and P6_REG.7:4.
Table 6-5. Bidirectional Port Control and Status Registers
Mnemonic Address
P1_DIR
1FD2H
P2_DIR 1FCBH
P5_DIR 1FF3H
P6_DIR 1FD3H
P1_MODE 1FD0H
P2_MODE 1FC9H
P5_MODE 1FF1H
P6_MODE 1FD1H
P1_PIN 1FD6H
P2_PIN 1FCFH
P5_PIN 1FF7H
P6_PIN 1FD7H
P1_REG 1FD4H
P2_REG 1FCDH
P5_REG 1FF5H
P6_REG 1FD5H
6.3.1

Bidirectional Port Operation

Figure 6-2 shows the logic for driving the output transistors, Q1 and Q2. Q1 can source at least
–3 mA at V – 0.7 volts. Q2 can sink at least 3 mA at 0.45 volts. (Consult the datasheet for spec-
CC
ifications.)
In I/O mode (selected by clearing Px_MODE.y), Px_REG and Px_DIR are input to the multiplex-
ers. These signals combine to drive the gates of Q1 and Q2 so that the output is high, low, or high
impedance. Table 6-6 is a logic table for I/O operation of these ports.
Port x Direction
Each bit of P x _DIR controls the direction of the corresponding pin.
0 = complementary output (output only)
1 = input or open-drain output (input, output, or bidirectional)
Open-drain outputs require external pull-ups.
Port x Mode
Each bit of P x _MODE controls whether the corresponding pin
functions as a standard I/O port pin or as a special-function signal.
0 = standard I/O port pin
1 = special-function signal
Port x Input
Each bit of P x _PIN reflects the current state of the corresponding
pin, regardless of the pin configuration.
Port x Data Output
For an input, set the corresponding P x _REG bit.
For an output, write the data to be driven out by each pin to the
corresponding bit of P x _REG. When a pin is configured as standard
I/O (P x _MODE. x =0), the result of a CPU write to P x _REG is
immediately visible on the pin. When a pin is configured as a
special-function signal (P x _MODE. x =1), the associated on-chip
peripheral or off-chip component controls the pin. The CPU can still
write to P x _REG, but the pin is unaffected until it is switched back to
its standard I/O function.
This feature allows software to configure a pin as standard I/O (clear
P x _MODE. x ), initialize or overwrite the pin value, then configure the
pin as a special-function signal (set P x _MODE. x ). In this way, initial-
ization, fault recovery, exception handling, etc., can be done without
changing the operation of the associated peripheral.
Description
I/O PORTS
6-5