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Name
Type
EPA9:0
I/O
EPORT.3:0
I/O
EXTINT
I
HLDA#
O
HOLD#
I
INST
O
Table B-4. Signal Descriptions (Continued)
Event Processor Array (EPA) Input/Output pins
These are the high-speed input/output pins for the EPA capture/compare
channels. For high-speed PWM applications, the outputs of two EPA channels
(either EPA0 and EPA1 or EPA2 and EPA3) can be remapped to produce a
PWM waveform on a shared output pin (see "Generating a High-speed PWM
Output" on page 10-16).
EPA9:0 are multiplexed as follows: EPA0/P1.0/T2CLK, EPA1/P1.1,
EPA2/P1.2/T2DIR, EPA3/P1.3, EPA4/P1.4, EPA5/P1.5, EPA6/P1.6, EPA7/P1.7,
EPA8/P6.0/COMP0, and EPA9/P6.1/COMP1.
Extended Addressing Port
This is a 4-bit, bidirectional, memory-mapped I/O port.
EPORT.3:0 are multiplexed with A19:16.
External Interrupt
In normal operating mode, a rising edge on EXTINT sets the EXTINT interrupt
pending flag. EXTINT is sampled during phase 2 (CLKOUT high). The minimum
high time is one state time.
If the chip is in idle mode and if EXTINT is enabled, a rising edge on EXTINT
brings the chip back to normal operation, where the first action is to execute the
EXTINT service routine. After completion of the service routine, execution
resumes at the the IDLPD instruction following the one that put the device into
idle mode.
In powerdown mode, asserting EXTINT causes the chip to return to normal
operating mode. If EXTINT is enabled, the EXTINT service routine is executed.
Otherwise, execution continues at the instruction following the IDLPD
instruction that put the device into powerdown mode.
EXTINT is multiplexed with P2.2 and PROG#.
Bus Hold Acknowledge
This active-low output indicates that the CPU has released the bus as the result
of an external device asserting HOLD#.
HLDA# is multiplexed with P2.6 and CPVER.
Bus Hold Request
An external device uses this active-low input signal to request control of the
bus. This pin functions as HOLD# only if the pin is configured for its special
function (see "Bidirectional Port Pin Configurations" on page 6-9) and the bus-
hold protocol is enabled. Setting bit 7 of the window selection register enables
the bus-hold protocol.
HOLD# is multiplexed with P2.5.
Instruction Fetch
This active-high output signal is valid only during external memory bus cycles.
When high, INST indicates that an instruction is being fetched from external
memory. The signal remains high during the entire bus cycle of an external
instruction fetch. INST is low for data accesses, including interrupt vector
fetches and chip configuration byte reads. INST is low during internal memory
fetches.
INST is multiplexed with P5.1 and SLPCS#.
SIGNAL DESCRIPTIONS
Description
B-7
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