Intel 8XC196NT User Manual page 165

8XC196NT USER'S MANUAL
Internal Bus
Px_REG
ADDRESS/DATA
BUS CONTROL SELECT
0=Address/Data
1=I/O
P34_DRV
Read Port
Figure 6-3. Address/Data Bus (Ports 3 and 4) Structure
When external memory access is not required, the device sets BUS CONTROL SELECT, select-
ing Px_REG as the input to the multiplexer. Px_REG then drives Q1 and Q2. If P34_DRV is set,
Q1 and Q2 are driven as complementary outputs. If P34_DRV is cleared, Q1 is disabled and Q2
is driven as an open-drain output requiring an external pull-up resistor.
6-16
1
0
Sample
Latch
Px_PIN
Q D
LE
PH1 Clock
300ns Delay
RESET#
Vcc
RESET#
Vss
150Ω to 200Ω
Buffer
Vcc
Medium
Pullup
Q3
Vcc
Weak
Pullup
Q4
Q1
I/O Pin
Q2
R1
A0240-03