Intel 8XC196NT User Manual page 323

8XC196NT USER'S MANUAL
Table 14-2. External Memory Interface Signals (Continued)
Function
Type
Name
EA# I External Access
EA# is sampled and latched only on the rising edge of RESET#.
Changing the level of EA# after reset has no effect. Accesses to
special-purpose and program memory partitions (FF2000H–
FF9FFFH) are directed to internal memory if EA# is held high and to
external memory if EA# is held low.
EA# also controls program mode entry. If EA# is at V
(typically +12.5 V) on the rising edge of RESET#, the device enters
programming mode.
NOTE: When EA# is active, ports 3 and 4 will function only as the
On devices with no internal nonvolatile memory, always connect EA#
to V
HLDA# O Bus Hold Acknowledge
This active-low output indicates that the CPU has released the bus
as the result of an external device asserting HOLD#.
HOLD# I Bus Hold Request
An external device uses this active-low input signal to request control
of the bus. This pin functions as HOLD# only if the pin is configured
for its special function (see "Bidirectional Port Pin Configurations" on
page 6-9) and the bus-hold protocol is enabled. Setting bit 7 of the
window selection register enables the bus-hold protocol.
INTOUT# O Interrupt Output
This active-low output indicates that a pending interrupt requires use
of the external bus. How quickly the 8XC196NT asserts INTOUT#
depends upon the status of HOLD# and HLDA# and whether the
device is executing from internal or external program memory. If the
8XC196NT receives an interrupt request while it is in hold and it is
executing code from internal memory, it asserts INTOUT# immedi-
ately. However, if the 8XC196NT is executing code from external
memory, it asserts BREQ# and waits until the external device
deasserts HOLD# to assert INTOUT#. If the 8XC196NT is executing
code from external memory and it receives an interrupt request as it
is going into hold (between the time that an external device asserts
HOLD# and the time that the 8XC196NT responds with HLDA#), the
8XC196NT asserts both HLDA# and INTOUT# and keeps them
asserted until the external device deasserts HOLD#.
INST O Instruction Fetch
This active-high output signal is valid only during external memory
bus cycles. When high, INST indicates that an instruction is being
fetched from external memory. The signal remains high during the
entire bus cycle of an external instruction fetch. INST is low for data
accesses, including interrupt vector fetches and chip configuration
byte reads. INST is low during internal memory fetches.
RD# O Read
Read-signal output to external memory. RD# is asserted only during
external memory reads.
14-4
Description
address/data bus. They cannot be used for standard I/O.
.
SS
Multiplexed
With
—
voltage
PP
P2.6
P2.5
P2.4/AINC#
P5.1/
SLPCS#
P5.3/
SLPRD#