Slave Port Functional Overview; Slave Port Signals And Registers - Intel 8XC196NT User Manual

8XC196NT USER'S MANUAL
Processor A
Processor A
9.1

SLAVE PORT FUNCTIONAL OVERVIEW

Figure 9-2 is a block diagram of the slave port. The slave port is a simple bus configuration that
can interface to an external processor through an 8-bit address/data bus (SLP7:0). The slave
8XC196NT processor communicates with the master (the external device) through the slave port
registers. From the slave viewpoint, the status register and data output register are output-only
registers that are latched onto the slave port address/data bus when SLPCS# and SLPRD# are
both low. The command register and data input register are input-only registers that are written
when SLPCS# and SLPWR# are both low.
9.2

SLAVE PORT SIGNALS AND REGISTERS

Table 9-1 lists the signals used for slave port operation. The bus-control output signals provided
by P5.3:0 in normal operation become inputs for slave port operation, and P5.4 functions as
SLPINT, the slave port interrupt signal. The P3.7:0 pins function as SLP7:0 to transfer byte-wide
information between the slave device and the master CPU. If external memory is to be used while
the slave port is enabled, external bus arbitration logic is required. Table 9-2 lists the registers that
affect the function and indicate the status of the slave port.
9-2
Dual-port
(Master)
(DPRAM)
(Master)
On-chip
RAM
Figure 9-1. DPRAM vs Slave-port Solution
Processor B
RAM (Slave)
Slave
8XC196 Device
A3065-01