Intel 8XC196NT User Manual page 464

Table A-8. Instruction Lengths and Hexadecimal Opcodes (Continued)
Mnemonic
Length
EBMOVI
ELD
ELDB
EST
ESTB
Mnemonic
Length
BMOV
BMOVI
LD
LDB
LDBSE
LDBZE
ST
STB
XCH
XCHB
NOTES:
1. Indirect normal and indirect autoincrement share the same opcodes, as do short- and long-indexed
modes. Because word registers always have even addresses, the address can be expressed in the
upper seven bits; the least-significant bit determines the addressing mode. Indirect normal and short-
indexed modes make the second byte of the instruction even (LSB = 0). Indirect autoincrement and
long-indexed modes make the second byte odd (LSB = 1).
For indexed instructions, the first column lists instruction lengths as S / L , where S is the short-indexed
2.
instruction length and L is the long-indexed instruction length.
3. For the SCALL and SJMP instructions, the three least-significant bits of the opcode are concatenated
with the eight bits to form an 11-bit, 2's complement offset.
Direct Immediate
Opcode Length
— — —
— — —
— — —
— — —
— — —
Direct Immediate
Opcode Length
— — —
— — —
3 A0 4
3 B0 3
3 BC 3
3 AC 3
3 C0 —
3 C4 —
3 04 —
3 14 —
INSTRUCTION SET REFERENCE
Data
Extended-indirect
Opcode Length
— 3
— 3
— 3
— 3
— 3
Indirect
(Note 1)
Opcode Length
— 3
— 3
A1 3
B1 3
BD 3
AD 3
— 3
— 3
— —
— —
Extended-
indexed
Opcode Length Opcode
E4 — —
E8 6 E9
EA 6 EB
1C 6 1D
1E 6 1F
Indexed
(Notes 1, 2)
Length
Opcode Opcode
S/L
C1 — —
CD — —
A2 4/5 A3
B2 4/5 B3
BE 4/5 BF
AE 4/5 AF
C2 4/5 C3
C6 4/5 C7
— 4/5 0B
— 4/5 1B
A-55