Intel 8XC196NT User Manual page 474

Table A-9. Instruction Execution Times (in State Times) (Continued)
Mnemonic
DJNZ
DJNZW
JBC
JBS
JC
JE
JGE
JGT
JH
JLE
JLT
JNC
JNE
JNH
JNST
JNV
JNVT
JST
JV
JVT
Mnemonic
NORML
SHL
SHLB
SHLL
SHR
SHRA
SHRAB
SHRAL
SHRB
SHRL
NOTE: The column entitled "Reg." lists the instruction execution times for accesses to the register file or
peripheral SFRs. The column entitled "Mem." lists the instruction execution times for accesses to
all memory-mapped registers, I/O, or memory. See Table 4-1 on page 4-2 for address information.
Conditional Jump
5 (jump not taken), 9 (jump taken)
6 (jump not taken), 10 (jump taken)
5 (jump not taken), 9 (jump taken)
5 (jump not taken), 9 (jump taken)
4 (jump not taken), 8 (jump taken)
4 (jump not taken), 8 (jump taken)
4 (jump not taken), 8 (jump taken)
4 (jump not taken), 8 (jump taken)
4 (jump not taken), 8 (jump taken)
4 (jump not taken), 8 (jump taken)
4 (jump not taken), 8 (jump taken)
4 (jump not taken), 8 (jump taken)
4 (jump not taken), 8 (jump taken)
4 (jump not taken), 8 (jump taken)
4 (jump not taken), 8 (jump taken)
4 (jump not taken), 8 (jump taken)
4 (jump not taken), 8 (jump taken)
4 (jump not taken), 8 (jump taken)
4 (jump not taken), 8 (jump taken)
4 (jump not taken), 8 (jump taken)
Direct
8 + 1 per shift (9 for 0 shift)
6 + 1 per shift (7 for 0 shift)
6 + 1 per shift (7 for 0 shift)
7 + 1 per shift (8 for 0 shift)
6 + 1 per shift (7 for 0 shift)
6 + 1 per shift (7 for 0 shift)
6 + 1 per shift (7 for 0 shift)
7 + 1 per shift (8 for 0 shift)
6 + 1 per shift (7 for 0 shift)
7 + 1 per shift (8 for 0 shift)
INSTRUCTION SET REFERENCE
Short-Indexed
Shift
A-65