Intel 8XC196NT User Manual page 140

PTS PWM Toggle Mode Control Block (Continued)
Register Location
PTSCON PTSCB + 1
Figure 5-16. PTS Control Block – PWM Toggle Mode (Continued)
Figure 5-17 is a flow diagram of the EPA and PTS operations for this example. Operation begins
when the timer is enabled (at t = 0 in Figure 5-15 on page 5-32) by the write to T1CONTROL.
The first timer match occurs at t = T1. The EPA toggles the output pin to zero and generates an
interrupt to initiate the first PTS cycle.
PWM Toggle Cycle 1. Because TBIT is initialized to one, the PTS adds the off-time (T2 –
T1) to EPA0_TIME and toggles TBIT to zero.
The second timer match occurs at t = T2 (the end of one complete PWM pulse). The EPA toggles
the output to one and generates an interrupt to initiate the second PTS cycle.
PWM Toggle Cycle 2. Because TBIT is zero, the PTS adds the on-time (T1) to
EPA0_TIME and toggles the TBIT to one.
The next timer match occurs at t = T2 + T1. The EPA toggles the output to zero and initiates the
third PTS cycle. The PTS actions are the same as in cycle 1, and generation of the PWM output
continues with PTS cycle 1 and cycle 2 alternating.
PTS Control Bits
M2:0 PTS Mode
These bits specify the PTS mode:
M2 M1 M0
0 1 0
TMOD Toggle Mode Select
1 = PWM toggle mode
TBIT Toggle Bit Initial Value
Determines the initial value of TBIT.
0 = selects initial value as zero
1 = selects initial value as one
The TBIT value determines whether PTSCONST1 or
PTSCONST2 is added to the PTSPTR1 value:
0 = PTSCONST1 is added to PTSPTR1
1 = PTSCONST2 is added to PTSPTR1
Reading this bit returns the current value of TBIT, which is
toggled by hardware at the end of each PWM toggle cycle.
STANDARD AND PTS INTERRUPTS
Function
PWM
5-35